1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a fin field effect transistor and method of forming the same.
2. Description of the Related Art
A fin field effect transistor (FinFET) such as a double gate MOSFET structure consists of a channel formed in a vertical silicon fin. FinFETs have found wide application as electronic devices for example, in digital processing applications. FinFETs, like other transistor devices, continue to be scaled to smaller and smaller dimensions in order to improve integrated circuit performance and cost. As the FinFET device is further miniaturized, device density will increase. It also becomes increasingly technically challenging to fabricate the FinFET features in the needed smaller dimensions.
The needed width of the fin structure is beyond the resolution limit or capabilities using the lithographic techniques currently available. Thus, fabrication methods different from the standard lithographic technique must be utilized. These techniques, which generally involves forming a larger silicon structure than desired for the final size, and then trimming the structure dimension through various means to the desired measure, have drawbacks that render them unacceptable. One such method of trimming oversize silicon fins involves an RIE (reactive ion etch) technique to trim down the silicon fin from its originally overdefined size. Thus, the technique is not viable for technology nodes going below that dimension. RIE is also an undesirable technique in that it generates fin structures with surface roughness. Surface roughness leads to poor electrical performance in the finished transistor.
U.S. Pat. No. 6,812,119 to Ahmed et al. discloses narrow fins by oxidation in double-gate FinFETs. The method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
There are, however, still some problems regarding overdefined size or surface roughness.